[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=132

--- Comment #39 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---


On Tuesday, January 7, 2020, Immanuel, Yehowshua U <yimmanuel3 at gatech.edu>
wrote:
> exactly how that's done given that Signal cannot at the moment be
> derived from (due to whitequark trying to early-optimise through use
> of "type", and not properly respect python coding conventions and
> warnings *sigh*) can i leave it to you to investigate?

Yes. I will add this to the pipeline.
Shouldn’t be too hard to come up with an inheritable structure for Partitioned
signals to be used with FMAs.

superb.

the ideal situation is this:

class Foo(Elaboratable):
def __init__ (self, SigKls):
     self.a = SigKls(32)

def elaborate(self, plat):
    ....
    m.comb += self.a + Const(5)


where we literally pass in Signal *or* PartitionedSignal as a parameter, and
regardless of which, the code will still work.

that means that PartitionedSignal.__add__ etc return some codefragments that
perform the partitioning.

actually, the first priority might just be to do a straight "passthrough" class
which pretty much only wraps Signsl's operators and constructor.

doesn't do any partitioning, just acts exactly like Signal, initially.

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