[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fsgnj/fsgnj.py;h=c43e180c0c55d6e12ee081a5b6e236aad6a1e554;hb=2352155642c82227e24e8782c6de61601938aa56

nice. have you done this before? :)

some comments on lines 44 46 48 for each of the opcodes would be nice.

and one around 42, "first do sign" or something then line 52, "then copy
mantissa/exp unmodified"

oh, also, line 41, Signals are all resetless.  the reason is because they are
combinatorial blocks, where the latches (pipelines) are reset.

actually because of the way the 6600 works they don't need it.  the 6600 DMs
isolate garbage during init.

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