[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/FPU.scala#L514

class FPtoFP.  what's going on there with widening-conversions, i have no idea,
given that the spec specifically says that NaN payloads are preserved

relevant part of spec:

Floating-point to floating-point sign-injection instructions, FSGNJ.S,
FSGNJN.S, and FSGNJX.S,
produce a result that takes all bits except the sign bit from rs1. For FSGNJ,
the result'ss sign bit is
rs2'ss sign bit; for FSGNJN, the result'ss sign bit is the opposite of rs2'ss
sign bit; and for FSGNJX,
the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection
instructions do not set
floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S
rx, ry, ry moves ry
to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the
negation of ry
to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry
moves the absolute
value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).

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