[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=ieee754fpu.git;a=commitdiff;h=2352155642c82227e24e8782c6de61601938aa56

that's funny, i watched the progression of the commits, i wondered how long it
would take to work out you could index by -1 to get at the sign bit for
arbitrary float length :)

there are other classes in FPBase i think which calculate the mantissa and
exponent offset and length etc. so that you don't have to hardcode those
values.

also if we want to FP8, FP80 or FP128 in the future no code has to change
except a one-line addition.

so, the last bit here: to check in the RISCV spec as to whether normalisation
needs to occur, certainly for F.MV i know it doesn't however for other ops i am
not sure.

one way to check is to track down the equivalent code for rocket-chip.

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