[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #11 from Michael Nolan <mtnolan2640 at gmail.com> ---
> let's keep this particular bugreport on topic though.

Alrighty

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