[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project.

[Staf Verhaegen]

whygee at f-cpu.org schreef op vr 10-01-2020 om 22:33 [+0100]:
> Hello Luke and list (Staf in particular)
> 
> On 2020-01-10 20:04, bugzilla-daemon at libre-riscv.org wrote:
> I've been working for a while on a gates library for my own use and it was pickedup by CERN because it's a free re-implementation of a proprietary library.https://ohwr.org/project/microsemi-lib (and they use ProASIC3 family chipsin particle accelerators because it's less sensitive than SRAM-based FPGA)
> What started as a tool to help me target a specific FPGA became a moregeneral tool to help with the gate-level design of my latest project :https://hackaday.io/project/162594-vhdl-library-of-proasic3-gates
> It could be more optimised for speed but would become more cumbsersome,I think the flexibility and the wide range of features make it very useful(I'm a speed freak but speed of development matters too, and any timeI start optimising something, it ends up in a publication 3 years later).
> It can be extended easily and simulated with the Free GHDL compiler,to help with DFT (Design For Test) : I can ensure functional verification(not formal verification, which is a different thing).The final goal is to let it create test vectors for on-wafer verificationbefore chips are packaged. I'm not there yet but it's already an invaluabletool that is worth the time I've spent on it, as I can get a more precisepicture of the gate delays and dependencies in a circuit (as well as checkthat the netlist is clean).
> Why do I suggest it ? The least that I can benefit from is :  - more tests and example designs to stress the code  - more gates and targets (the core code can manage 4-inputs gates        though I don't use them, yet)  - linking the work to other families/technologies, ASIC gates in particular,       because my projects aim at silicon (FPGA is just for mock-ups)  - if all goes well, my CPU projects could use the ASIC Cell Libraries       Luke mentions in the original post, which could be used as a       reasonably small and well-controlled guinea pig before going       to larger designs, such as the FP units.
> Some synthesisers (such as Actel/MicroSemi/Microchip's) can outputa working VHDL netlist, I might one day tweak the system to parse EDIF(VHDL is a real language, you know, I write awesome things with that)
> So it's really a "backend tool" and "early functional verification tool",it's free, self-contained, flexible and useful.
> What do you think ?

When doing DFT for ASIC current tools rely on having flip-flops with scan chain support. That feature is then used to load test patterns in the design and test the chip. What I do think you propose is to not only use flip-flops with scan chain support but extend the functionality of the standard cells for DFT. Unfortunately I don't see how you can do this without introducing unwanted area overhead for ASICs.
Given the timeline for the NLNet project DFT was not included and testing is planned to be done in the old way by just running test programs and see if they have the right output.

greets,
Staf.