[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fcvt/int2float.py;h=fcf3e34cf3025b02995b76251d363834640b7deb;hb=HEAD

right.  copy that, aaall of it, calk it fcvt.py or something in a new
subdirectory ieee754/fcvt, rename as appropriate (global search replace). 
replace lines 32 to 119.

lines 18 and 19 set up a 2 bit op comment, 0x3 == 0b00 / 0b01 / 0b10 for mv,
abs, neg.

https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fcvt/pipeline.py;h=5e6cc19dee7f98c971d1ea7e2266339b4bf4d2ec;hb=HEAD

copy this except delete lines 117 onwards and search/replace FPCVTF2IntMuxInOut
with  the new fcvt class name.

i am goung to have to think how the classes stack together (it's been a while)
leave that with me

an __init__.py is necessary.

the test dir gets copied too, cooy just this file

https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/fcvt/test/test_fcvt_f2int_pipe.py;h=4e01d8c2bc6915a6465162eae48decdeb710645f;hb=HEAD

now you should notice there, opwidth has to be set to 2 because, duh, you have
3 ops, 0b00 0b01 and 0b10

and to test them each you have to set opcode=....

the callback function in the unit test obviously has to change.

if you do this:
$ python3
>>> from sfpy import Float32
>>> x = Float32(1.0)
>>> dir(x)

you will get a list of functions, you're looking for bits (for mv), a sgn
function and an abs function.

those give you the function to call in the test converters see lines 10 to 68
all of which you replace with fsgn_mv_f32_to_f32 etc etc etc etc.

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