[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #3)

> From what I recall, the state-machine modules were added to serve as a
> reference for conversion to pipelined form. 

pretty much. i used them as stepping stones in a looong incremental conversion
process, making sure there was always something to test at all times.  it was a
pig :)

> The RISC-V sign-manipulation
> instructions are simple enough that they can be a single-stage pipeline.

yes.

-- 
You are receiving this mail because:
You are on the CC list for the bug.