[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #2)
> I'd like to take a stab at this, 

cool!  this is pretty easy, not rocket science.

> however I'm not sure where to put it.

start cookie-cut from e.g. the fclass one or the fcvt int to float one.

> Should it be made a separate module in the ieee754 directory 

yes.

> or should it go
> somewhere else (like part of an existing module?)

no, see hdl_workflow

> Also, I've been looking through the FPU modules and I've noticed there are
> two "styles" of modules:
> 
>  - Pipelined - like fpmul/pipeline.py
>  - State machine - like fpmul/fmul.py

yes. right. i was experimenting. a lot. the idea was, FSM or pipeline, it's not
your decision, you just create combinatorial building blocks and the user
decides how to join them together.

it worked, but got complicated and i left it for another day. leave FSM for
now.


> Since this module is only a couple of gates and can be combinatorial, I'd
> imagine it should probably have a similar interface to the state machine
> variety, but I'm not sure.

you'll see on inspecting the (simpler) fcvts that it's mostly setup blurb.

gimme sec let me find some links on git.libre-riscv.org and illustrate

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