[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Michael Nolan from comment #2)
> Also, I've been looking through the FPU modules and I've noticed there are
> two "styles" of modules:
> 
>  - Pipelined - like fpmul/pipeline.py
>  - State machine - like fpmul/fmul.py
> 
> Since this module is only a couple of gates and can be combinatorial, I'd
> imagine it should probably have a similar interface to the state machine
> variety, but I'm not sure.

>From what I recall, the state-machine modules were added to serve as a
reference for conversion to pipelined form. The RISC-V sign-manipulation
instructions are simple enough that they can be a single-stage pipeline.

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