[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

Michael Nolan <mtnolan2640 at gmail.com> changed:

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                 CC|                            |mtnolan2640 at gmail.com

--- Comment #2 from Michael Nolan <mtnolan2640 at gmail.com> ---
I'd like to take a stab at this, however I'm not sure where to put it. Should
it be made a separate module in the ieee754 directory or should it go somewhere
else (like part of an existing module?)

Also, I've been looking through the FPU modules and I've noticed there are two
"styles" of modules:

 - Pipelined - like fpmul/pipeline.py
 - State machine - like fpmul/fmul.py

Since this module is only a couple of gates and can be combinatorial, I'd
imagine it should probably have a similar interface to the state machine
variety, but I'm not sure.

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