[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #9 from Michael Nolan <mtnolan2640 at gmail.com> ---
> i need your agreement (on-list) to the charter, first.

I (just now) replied to the HDL Workflow thread with my agreement.

> that's a little trickier as it's outside of everyone currently in the teams' experience.

I should probably have mentioned this in my intro post, but I have some
experience with formal verification (the yosys flavor anyway). Provided the
pipeline control signals don't screw things up too much, it should be pretty
straightforward.

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