[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #20 from Michael Nolan <mtnolan2640 at gmail.com> ---
> correct.  the partition mask will at some point be passed in through a
> Mix-In class such that there should be very little in the way of changes.

That's pretty neat!

> the block "proc group_0" is where the switch/case statement is, which
> needs replacing with some Mux()es.  those will basically be:

>   Mux(op[1],
>       Mux(op[0], 0b11 calculation, 0b10 calculation),
>       Mux(op[0], 0b01 calculation, 0b00 calculation)
>      )

I added something like this on my latest commit. However I defined the behavior
of opcode 0b11 to be the same as 0b10 (Saving 1 mux in the process). Since the
RISCV spec doesn't define the behavior of opcode 0b11, this seems safe to do
(right? Rocket does it)

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