[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #17)
> > the reason is down to the deployment of the PartitionedSignal class, which
> > will perform operations in parallel.  to support m.Case(), m.If() etc. we
> > would need to do a seeerious amount of coding, possibly even modifying
> > nmigen itself.
> 
> So what you're saying is: If(), Switch() and friends are fine for modules
> that are strictly scalar, but will not work if the module is converted to
> SIMD.

correct.  the partition mask will at some point be passed in through a
Mix-In class such that there should be very little in the way of changes.

> > apologies i forgot to mention that.
> 
> All good

btw if you want to see the actual gate-level graph, which i highly
recommend getting into the habit of doing, install graphviz and xdot
and use this:

    yosys
    > read_ilang test_fsgnj_something_something.il
    > show top

or type "show <tab> <tab>" to get a list of modules.  the one you want
is fsgnj$4

you can see it here:
http://bugs.libre-riscv.org/attachment.cgi?id=19

what you've written basically falls very neatly into the "acceptably
small size range such that it's easy to see what's going on and also
will be dead-easy to do the layout for using alliance/coriolis2"

the block "proc group_0" is where the switch/case statement is, which
needs replacing with some Mux()es.  those will basically be:

   Mux(op[1],
       Mux(op[0], 0b11 calculation, 0b10 calculation),
       Mux(op[0], 0b01 calculation, 0b00 calculation)
      )

something like that, where 0b11 will be "default" err i think.

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