[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #17 from Michael Nolan <mtnolan2640 at gmail.com> ---
> the reason is down to the deployment of the PartitionedSignal class, which
> will perform operations in parallel.  to support m.Case(), m.If() etc. we
> would need to do a seeerious amount of coding, possibly even modifying
> nmigen itself.

So what you're saying is: If(), Switch() and friends are fine for modules that
are strictly scalar, but will not work if the module is converted to SIMD.

> apologies i forgot to mention that.

All good

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