[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
*click*, apologies michael: i just realised something.  although Switch/Case
statements ultimately map down to Mux() or in rare cases PMux, for the FPU code
we can't use them.... or If() statements (basically anything with a "with" 
context).

the reason is down to the deployment of the PartitionedSignal class, which
will perform operations in parallel.  to support m.Case(), m.If() etc. we
would need to do a seeerious amount of coding, possibly even modifying
nmigen itself.

by keeping to Mux as a decision-maker plus basic arithmetic operators we
can write a parallel-PartitionSignal-aware-Mux() plus parallel-aware arith
and the job of converting all code to dynamic SIMD is a by-the-numbers
process pretty much replacing Signal with PartitionedSignal across all FP
classes.

apologies i forgot to mention that.

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