[libre-riscv-dev] Possible nMigen Milestone?

[whygee at f-cpu.org]

On 2020-01-07 02:55, Luke Kenneth Casson Leighton wrote:
> the cycle time on e.g. FPDIV is around 2 sim clocks per second, and
> the partitioned INT multiplier is around the same.
> 
> that's *without* the partitioning, and without even linking any of
> this together into an actual processor.
> 
> *combine* the partitioned INT mul code into say FPMUL or FPMAC and we
> could well be looking at seconds to tens of seconds per sim-clock
> tick.
> 
> the simulation times, without some kind of drastic performance
> increase, are going to be awful :)  so i am veeery glaad you and
> whitequark have been working on this.  it'll just be around the right
> time, too.

How large is this design ???

So far my methodology is to use pure VHDL.
Staying with only one langage (and a potent one)
that uses LLVM/GCC optimisation backends,
a clean and flat programming (instead of
russian dolls) has proven quite efficient for me...
I could test kilovectors per second and I didn't
even push much (I could have saved time by ...
not restarting GHLD for every damned vector
AND using all 4 cores)

KISS :)

> l.
yg