[libre-riscv-dev] openrisc1200

[Immanuel, Yehowshua U]

> we should try to keep our messaging more consistent, continuously changing
> which ISA we will use will cause people to not think we will ever complete
> anything

I agree with Jacob - however, filling in the table is a exercise - and we can refer future 
contributors to the table in the future.

> Power is known to be very suitable for high-performance CPUs (Power9).

This also is quite true.
Also note, that while I’m sure we are all capable of adding user land and compiler support for an arbitrary CPU,
we should minimize the software component and maximize the hardware component of our effort vector.

> Power has a huge software ecosystem, probably larger than all of RISC-V,

If this is true, than why would we wish to support the RISCV-V Dual ISA? We should just stick with POWER.

Yehowshua 

> On Jan 21, 2020, at 10:16 AM, Jacob Lifshay <programmerjake at gmail.com> wrote:
> 
> On Tue, Jan 21, 2020, 02:42 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
> 
>> https://libre-riscv.org/3d_gpu/arch_comparison/
> 
> 
> I added data for a lot more aspects. I think that we should go with
> OpenPower due to several aspects:
> 
> 
> 
> 
> MIPS, and OpenRISC combined. Probably the 3rd largest in the industry after
> x86 and ARM. This is probably the biggest factor for which ISA to pick.
> 
> 
> 
> OpenRISC doesn't seem to be a viable option due to the lack of support for
> 64-bit in software (linux, probably others), among other reasons.
> 
> more reasons in the table on the wiki page.
> 
> Jacob
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