[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=155

Jacob Lifshay <programmerjake at gmail.com> changed:

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--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #0)
> https://github.com/ZipCPU/dpll

I'm guessing that's not the kind of PLL you wanted, it's intended for creating
lower frequency sine waves that match a reference sine wave by running a
counter off a much higher speed digital clock, adjusting the counter's trip
count, and running the counter's output to a sin() lookup table. It's intended
for something like audio processing, from what I can tell.

Assuming you want a PLL for generating high-frequency (>500MHz) digital clocks,
you'd have to use a different method, such as using an analog VCO for the PLL.

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