[libre-riscv-dev] Possible nMigen Milestone?

[Immanuel, Yehowshua U]

I notice you were trying to convert verilog to nMigen here:

http://bugs.libre-riscv.org/show_bug.cgi?id=72

Do you think we could instead directly embed verilog into nMigen instead of converting it to nMigen?

https://github.com/m-labs/nmigen/issues/1

Also, with the verilator backend, we can directly simulate nMigen and verilog together. I think this is a valid approach because nMigen would emit the verilog as EDA tools would see it.