[libre-riscv-dev] Possible nMigen Milestone?

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Mon Jan 6 19:39:37 GMT 2020

I notice you were trying to convert verilog to nMigen here:


Do you think we could instead directly embed verilog into nMigen instead of converting it to nMigen?


Also, with the verilator backend, we can directly simulate nMigen and verilog together. I think this is a valid approach because nMigen would emit the verilog as EDA tools would see it.

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