[libre-riscv-dev] Possible nMigen Milestone?

[Luke Kenneth Casson Leighton]

On 1/6/20, Immanuel, Yehowshua U <yimmanuel3 at gatech.edu> wrote:
> I notice you were trying to convert verilog to nMigen here:
>
> http://bugs.libre-riscv.org/show_bug.cgi?id=72
>
> Do you think we could instead directly embed verilog into nMigen instead of
> converting it to nMigen?

of course... except:
1. it can't then be run as a nmigen simulation, and
2. if it is not completely and wholly and 100% suited precisely and
exactly to our requirements, it needs modification

> https://github.com/m-labs/nmigen/issues/1
>
> Also, with the verilator backend, we can directly simulate nMigen and
> verilog together.

yes.  we will have to do that when it comes to adding peripherals.

> I think this is a valid approach because nMigen would emit
> the verilog as EDA tools would see it

verilog is used exclusively by *proprietary* EDA tools (for verification etc.)

when you use alliance / coriolis2 or magic and so on, verilog is no
longer the primary sole exclusive EDA route to a VLSI layout.

l.