[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=137

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to cand from comment #2)
> Each codec then has these phases:
> - research
> - for each hotspot, implementation
> - for each target library, upstreaming

ok great, do you have an estimation of time (and budget you'd like to receive)
for each? 1 week research, 2 week impl, 3 day upstream coordination, that sort
of thing?

we can subdivide later (3 subbugs per each top bug) if you would like
part-payment however that is for later.

the focus now is to identify toplevel and assign budgets. 

> HW implementations of new instructions would be later, once the instructions
> are known.

yes.  or, more to the point, you advise us what you would like, then we
implement them in a simulator (which we have to budget how to run under that,
btw - it may be that we only run a subset of the code, say, only the algorithm
or a unit test rather than full VLC or sonething)

then after the cycles/sec is confirmed *then* we implement that opcode in hw
and finally actually run under an FPGA.  this will be much later, at the end of
the process.

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