[libre-riscv-dev] Wishbone Arbiter

[Luke Kenneth Casson Leighton]

On Sun, Jan 26, 2020 at 11:56 PM <whygee at f-cpu.org> wrote:

> for more than 40 years, screen refresh is also performed by refreshing
> the DRAM,
> can this be done here too ?

my understanding of DRAM is that its charge is topped up by doing a
scan-read.  i have vague recollections of a row scan being sufficient.

thus with screen dram reads being also sequential and repeated,
they're effectively doing double duty.

however for shared memory architectures (there will be no separate
screen DRAM) the LCD reads are focussed solely on the DDR3/4 memory
area where the framebuffer resides.

therefore the rest of that DDR3/4 memory, not including the
framebuffer area, woud still need scanning refreshes.  not that i know
exactly how that works in DDR memory land.

l.