[libre-riscv-dev] Wishbone Arbiter

[whygee at f-cpu.org]

On 2020-01-27 01:17, Luke Kenneth Casson Leighton wrote:
> On Sun, Jan 26, 2020 at 11:56 PM <whygee at f-cpu.org> wrote:
> 
>> for more than 40 years, screen refresh is also performed by refreshing
>> the DRAM,
>> can this be done here too ?
> 
> my understanding of DRAM is that its charge is topped up by doing a
> scan-read.  i have vague recollections of a row scan being sufficient.
> 
> thus with screen dram reads being also sequential and repeated,
> they're effectively doing double duty.
> 
> however for shared memory architectures (there will be no separate
> screen DRAM) the LCD reads are focussed solely on the DDR3/4 memory
> area where the framebuffer resides.
> 
> therefore the rest of that DDR3/4 memory, not including the
> framebuffer area, woud still need scanning refreshes.  not that i know
> exactly how that works in DDR memory land.

it's a matter of interleaving correctly, and mapping lines and such.

DRAM is refreshed when you close a DRAM line, so you just select one,
it is copied in a buffer, you migh read individual bytes or not,
and then the write-back refreshes the cells on close.

Depending on how you permute address bits and allocate banks,
a simple DMA (with some FIFO buffer) would refresh both the DRAM and the 
LCD.
Then it depends on the DRAM organisation/size, and LCD resolution...

read you tomorrow :-)

> l.
yg