[libre-riscv-dev] Wishbone Arbiter

[Jacob Lifshay]

On Sun, Jan 26, 2020, 16:48 <whygee at f-cpu.org> wrote:

> DRAM is refreshed when you close a DRAM line, so you just select one,
> it is copied in a buffer, you migh read individual bytes or not,
> and then the write-back refreshes the cells on close.
>
> Depending on how you permute address bits and allocate banks,
> a simple DMA (with some FIFO buffer) would refresh both the DRAM and the
> LCD.
> Then it depends on the DRAM organisation/size, and LCD resolution...
>

It seems like a bad idea to link video scanout to DRAM refreshing, video
can be disabled for some reason (changing video modes, suspend-to-ram,
output disconnected, etc.), that shouldn't cause the DRAM to stop
refreshing.

I had been thinking that DRAM refreshing would be handled by a refresh
counter in the DRAM controller, after all, a temporary video blip is much
better than crashing due to corrupted ram.

Jacob

>