[libre-riscv-dev] Why The Dual ISA

[Jacob Lifshay]

On Sun, Jan 19, 2020, 10:41 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Monday, January 20, 2020, Adam Van Ymeren <adam at vany.ca> wrote:
>
> >
> > That conversation may be easier to have now rather than after receiving
> > another year or two of funding.  It's not just the added work of
> > supporting dual-ISA.  Every decision made going forward on the design
> > will be influenced by this need to support dual-ISA whether consciously
> > or not.  A year spent trying to build dual-ISA _could_ be worth 2 years
> > spent building just one.
>
>
> decoders for RISC architectures simply do not take that long to write.
>
> the CSRs etc may be more challenging.
>

The only RISC-V CSR we *need* HW support for is the fp control/status csr,
the rest can be effectively implemented using trap and emulate, assuming
we're aiming for being able to run rv64gc (standard RISC-V unix ABI)
user-mode at full speed and emulate supervisor/hypervisor/machine modes.
The rv64gc programs would run on a ppc64le Linux kernel with appropriate
modifications (anticipating few thousand lines of Linux code for basic
user-mode support which includes ability to have both rv64gc and ppc64le
code in the same Linux process).

Being able to run both RISC-V and Power code in the same process is a
*huge* advantage, the only other spot I can recall something like that is
Wine/Windows WoW64 running x86-32 with x86-64 code, which is much more
limited in that you can't really call between 32 and 64-bit code in user
code, and x86-32 and x86-64 are much more closely related.

Jacob