[libre-riscv-dev] Why The Dual ISA

[whygee at f-cpu.org]

On 2020-01-19 20:23, Adam Van Ymeren wrote:
>> decoders for RISC architectures simply do not take that long to write.
>> 
>> the CSRs etc may be more challenging.
>> 
>> we will have to see.
>> 
>> l.
> 
> Good point, this whole conversation may be moot, as its really not much
> of a problem.  Sorry for adding to the noise.

decoding by itself is not really hard, but scheduling and getting 
everything
to work together in harmony is another can of worm however.
POWER is designed explicitly for OOOe and is not obvious from the start.

The POWER ISA supports "embedded" platforms but the little I remember 
about the PPC era
(I had a book describing the 601, 603 and maybe 620) confused me a 
lot...
POWER needs a good high-level introduction to the architecture, coding 
and ISA.

> -Adam
yg