[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Yehowshua from comment #14)
> I recently came across pyverilog which will parse verilog(not sure how
> robust its sv capabilities are).
> 
> https://github.com/PyHDI/Pyverilog

interesting.  i started with python-ply because i know it is extremely good (i
do a *lot* of language translation), so what they have done, is already taken
care of.

as i know lex syntax from my time in university i added the required sv support
(which was primarily the ability to use types in module interface declarations)
very quickly.

> Why are we converting verilog into nMigen?

because the code being targetted for conversion (the ariane project) requires
significant modification, and, more than that, absolutely nobody in the
software libre world - because it is specifically and critically dependent on a
*proprietary* verilog toolchain - can use it.

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