[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #18 from Tobias Platen <hacks2019 at platen-software.de> ---
I have tried pyverilog. It seems to work for the Xilinx dialect, but it seems
to fail for the SystemVerilog dialect that ariane uses.

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