[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Tobias Platen from comment #18)
> I have tried pyverilog. It seems to work for the Xilinx dialect, but it
> seems to fail for the SystemVerilog dialect that ariane uses.

yes.  it is a mentor graphics augmented nonstandard SV that allows structs in
the module parameters.

i had to modify the parser to get it to work.

actually it is incredibly sensible what they did, otherwise module declarations
can have hundreds of parameters, which is extremely tedious and errorprone.

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