[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #16 from Yehowshua <yimmanuel3 at gatech.edu> ---
see:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003261.html

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