[libre-riscv-dev] Possible nMigen Milestone?

[Immanuel, Yehowshua U]

I found some of the NlNet milestones here and realized a number of them are related to nMigen features.
Since I have plenty experience in nMigen, I’ll start working on those next week.

http://bugs.libre-riscv.org/buglist.cgi?=%20&action=wrap&cf_nlnet_milestone=NLnet.2019.02&resolution=---

This got me thinking - I’ve been working on the verilator backend for nMigen - could this be a possible milestone?

The way the verilator backend works is:
1. it first has nMigen emit verilog 
2. it then collects all the port signals from the hdl.generate.verilog class
3. it generates verilog dpi read/write functions for all these signal 
4. it generates corresponding C DPI access functions
5. all this is built into a shared object with verilator and imported with python Ctypes(all the wire/signal sizes are analyzed to make sure that python passes arrays of correct length for longer signals etc.)
6. All the Tick(), Setlle(), Delay() etc. commands are re-implemented according to whitequark's original PySim spec.

The benefit of verilator is not only speedy simulation, but testing your design directly on the emitted verilog, which is what will be used in EDA floor planning.

What are your thoughts?