[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=70

--- Comment #8 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #7)
> From reading the spec, tilelink seems to be a relatively simple (20-30
> states) state machine along with a 64-bit
> Add/CompareEq/Min/Max/MinU/MaxU/And/Or/Xor ALU for handling AMOs. I would be
> surprised if TileLink needed more than 2-3k gates.

Turns out CompareEq is not supported -- I had forgotten that RISC-V doesn't
have a compare-exchange operation.

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