[libre-riscv-dev] [Bug 70] evaluate Bus Architectures

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=70

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
when multiple reference implementatiobs are available it will save us a huge
amount of time and help us to ensure interoperability.

until then, unfortunately, the cost is i feel too high.  it's a brilliant idea,
not to be ruled out entirely: we may even need to span across multiple FPGAs
and ethernet is one of the easiest ways to do that.

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