[libre-riscv-dev] Wishbone Arbiter

[Luke Kenneth Casson Leighton]

On 1/26/20, Tobias Platen <tplaten at posteo.de> wrote:
> I just had to look into the nmigen-soc repo.
> The latest pull request[1] adds an arbiter, which I have not understood yet.

you have to have a many-to-one and a one-to-many.  this is part of the
IO Handling library's more advanced features.

otherwise when you have multiple peripherals, um... how are you going
to route them?  put everything onto a single global bus? (ans: i don't
think so).

instead what is done is:

* *slow* peripherals are put onto their own global bus, managed by a
single "Master"
* *fast* peripherals are made a "Bus Master" (such as the LCD / VGA driver)
* the L1 caches are also placed onto their own "Bus"

and all three "Buses" are "multiplexed" onto a single channel, to
which the L2 and memory are connected.  that single channel is
"arbitrated" because, duh, otherwise, you end up with clashes on the
bus as multiple devices try to read/write simultaneously.

this is outlined (implicitly) in the diagram i drew here
https://libre-riscv.org/shakti/shakti_libre_riscv.jpg although not
very well, now that i look at it.

btw the LCD / VGA ABSOLUTELY HAS to be ABSOLUTE top priority,
over-and-above ABSOLUTELY everything else.  if the LCD driver cannot
get the next scan line from DDR memory, to drive the LCD signals, the
screen display is absolutely hosed: you get white-outs, flicker, snow
and worse.

l.