[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

Yehowshua <yimmanuel3 at gatech.edu> changed:

           What    |Removed                     |Added
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                 CC|                            |yimmanuel3 at gatech.edu

--- Comment #14 from Yehowshua <yimmanuel3 at gatech.edu> ---
I recently came across pyverilog which will parse verilog(not sure how robust
its sv capabilities are).

https://github.com/PyHDI/Pyverilog

Why are we converting verilog into nMigen?

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