[libre-riscv-dev] Possible nMigen Milestone?
Immanuel, Yehowshua U
yimmanuel3 at gatech.edu
Mon Jan 6 21:58:15 GMT 2020
> what's been done, what's left, and how long will it take to completion
> for stable production use?
Steps one through 5 work. Tick() and Settle() in 6 work.
7. Support for multiple synchronous domains in waveform generation
8. Timekeeping for writing waveforms
9. Plugging Pysim into verilator backend for to evaluate expressions inside yield - fairly low priority
I’ve been communicating with Whitequark and I think Verilator backend would be upstream and production ready by the beginning of March if not earlier.
I should also add that whitequark is adding a C++ yoys(CXXSim) based backend that has been shown to be reasonably fast in its own right.
I thought the verilator backend might solve the problem with needing to convert verilog to nMigen - but I now know that is not the case.
So the only advantage I see the verilator backend bringing to the table is its multithreaded capabilities which might come in handy with later arithmetic intense simulations.
> 1) squeeze this in to an existing project. we can potentially get
> away with this if the (remaining) work needed is small and *clearly*
> fits *directly* into it.
> 2) put in a new funding application.
I conclude that the verilator backend is not directly necessary for the project goals. This is fine, there are some other tasks that need attention.
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