[libre-riscv-dev] architecture page

[Luke Kenneth Casson Leighton]

On 1/26/20, Tobias Platen <tplaten at posteo.de> wrote:

>> >> https://libre-riscv.org/3d_gpu/architecture/
>> > There is no mention of memory or caches, I think that should be written
>> > next.
>> > Maybe on its own subpage.
>>
>> good idea, stubs created.
> looks good, I'll expand it later

great.  remember we have to follow Power ISA TLB / MMU rules, not RISC-V now.