[libre-riscv-dev] POWER / RV dual interoperability

[Luke Kenneth Casson Leighton]

On Sun, Jan 19, 2020 at 2:09 AM Hendrik Boom <hendrik at topoi.pooq.com> wrote:

> On Sat, Jan 18, 2020 at 10:15:52PM +0100, whygee at f-cpu.org wrote:
>
> > Some are already looking at POWER... but with a dual ISA
> > (or "why make it simple when it can be complex ?")
>
> A dual ISA will force you to keep a lot of the internals simple.
> They cannot involve kludges for one ISA or the other.
>

indeed.

we need a micro-code system anyway, because of the translation between
front-end "Vector-loop" and back-end "SIMD-with-predication-and-more".

adding an extra ISA front-end is child's play - apart from the
only-slightly-annoying differences in the FP exceptions and how FP numbers
are implicitly converted in Power to the full 64-bit.  as in: a 32-bit
number is *never* stored as a 32-bit number in Power FP regs: it is
*always* converted to a 64-bit FP number.

there's other quirks such as how to deal with carry in vector addition
(etc.) because we are looking to do "assume that vectors are basically a
hardware for-loop issuing SEQUENTIAL scalar instructions" and of course
that would mean that carry flags have to respected *inter-vector-elements".

with RISC-V, because there *is* no carry bit, the above strategy is
perfectly fine.  all ADDs all MULs etc. are independent.

of course, it means that if you want to do bigint math, it's a frickin
nuisance on RV, however it is "simpler".

remember the quote, by einstein, "it should be as simple as needed and no
simpler"?

l.