[libre-riscv-dev] Yehowshua - Interested in open GPU dev

[Luke Kenneth Casson Leighton]

On 1/6/20, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> you get the general idea, i'm sure.  it's quite a neat, self-contained
> elegant task.

http://bugs.libre-riscv.org/show_bug.cgi?id=132

ah!  found that bugreport, now, too.

yehowshua, could we move discussion onto that bugreport, to keep
proper track?  you've probably noticed by now that the bugtracker ccs
the mailing list (for convenience) however it's not 2-way.

you can see e.g. from comment #36 that the code in the FPU has been
"prepared", through the removal of all if/else statements, to use Mux.

by providing a Partition-aware "Mux" (plus others) the intent is that
we can literally keep the FPU codebase absolutely identical, then pass
in a class - Signal or PartitionedSignal - depending on whether the
end-user wants a "straight" FPU or a "SIMD Partitionable" FPU (or even
a degenerate-case of static partitioning, a "normal SIMD" FPU).

l.

p.s. continuing the answer about "why use nmigen not verilog", try
thinking through how to do a dynamic-partitionable reconfigureable FPU
in verilog.