[libre-riscv-dev] [Bug 154] Cell for Dependency Matrices is needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=154

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #12)
> (In reply to Luke Kenneth Casson Leighton from comment #11)
> > (In reply to Staf Verhaegen from comment #8)
> > > (Sorry accidently commit previous comment. Redo comment)
> > > 
> > > After reading a little further I think that the architecture was developed
> > > at a moment where not the current synthesis, place-and-route and timing
> > > check tools were available. 
> > 
> > yes. i need to get back to Taiwan and update everything. so much has
> > happened even in 8 months.
> 
> I was talking about the CDC6600 architecture...

oh! yes, haha, yes absolutely.  writing for benefit of list archives here:
google "Design of a Computer, James Thornton".

they used ECL logic, they used *actual transistors* (3 pins, thru-hole), and
did the entire design over several years, on paper, *waiting for that
transistor to be invented*

how stunning is that.

Mitch's book then "converts" that ECL logic into standard ISO gates, and, with
a *lot* of help i was able to replicate it.

Mitch is one of the last people left on the entire planet with the crossover
knowledge between the very early supercomputer days and modern EDA design. 
even he still only does gate-level design, not verilog.

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