[libre-riscv-dev] [Bug 130] FMIN/MAX needed

[Luke Kenneth Casson Leighton]

nmigen/hdl/ast.py:

"AnyConst", "AnySeq",

        # connect up the inputs and outputs. I think these could
        # theoretically be $anyconst/$anysync but I'm not sure nmigen
        # has support for that

answer, yes.

On 1/28/20, bugzilla-daemon at libre-riscv.org
<bugzilla-daemon at libre-riscv.org> wrote:
> http://bugs.libre-riscv.org/show_bug.cgi?id=130
>
> --- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> yeah go for it.  here's the scala reference code:
> https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/FPU.scala#L530
>
> --
> You are receiving this mail because:
> You are on the CC list for the bug.
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>