[libre-riscv-dev] Beginning Steps and Deadlines

[Luke Kenneth Casson Leighton]

On Sunday, January 5, 2020, Immanuel, Yehowshua U <yimmanuel3 at gatech.edu>
wrote:

> I’ve browsed through the git repos and have a decent idea of what’s going
> on here.


superb.

if you email me an ssh public key i can at least get you set uo. no rush
there.

the biggest piece of work is the IEEE754 FPU.  woo :)

that is not only going to be auto-SIMD-partitionable (the INT MUL already
is) it is a dynamic length pipeline as well.

so we can do say 4 stage at 800 mhz and save power and keep latency down
however if we want to do 1600mhz we close some gates which splits stages in
half, now it is *8* stage.

basically every pipeline register latch has a MUX bypass on the front.

IBM first documented this trick.

l.



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