[libre-riscv-dev] Why The Dual ISA

[Jacob Lifshay]

On Sun, Jan 19, 2020, 01:08 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> the "state" would also include the *value* of predication bits, rather than
> the *register* in which that predication is stored.
>

I think we should also support running a side-effect free instruction (no
stores, no loads not in L1) before the predication bits are known, then
skip writing unneeded results once the predicate bits are known, this will
allow us to increase performance by utilizing ALUs that otherwise would run
a NOP, reducing latency.

Jacob

>