[libre-riscv-dev] Why The Dual ISA

[Jacob Lifshay]

On Sun, Jan 19, 2020, 05:55 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Sunday, January 19, 2020, Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > On Sun, Jan 19, 2020, 01:08 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > wrote:
> >
> > > the "state" would also include the *value* of predication bits, rather
> > than
> > > the *register* in which that predication is stored.
> > >
> >
> > I think we should also support running a side-effect free instruction (no
> > stores, no loads not in L1) before the predication bits are known, then
> > skip writing unneeded results once the predicate bits are known, this
> will
> > allow us to increase performance by utilizing ALUs that otherwise would
> run
> > a NOP, reducing latency.
>
>
> i apologise, it's been a year now already and i git sidetracked into the
> IEEE754FPU for several months.  below is from memory.
>
> what i had implemented, or planned, was something that involves "shadowing"
> that is not similar to branch prediction shadowing, it is identical to
> branch prediction shadowing.


Yeah, I remember now.

Thanks, Jacob