[libre-riscv-dev] Some general instruction ideas

[whygee at f-cpu.org]

On 2020-01-24 17:19, Immanuel, Yehowshua U wrote:
> That said - what’s the RISC way of Memcopy?

I doubt there is "a RISC way".

> probably:
> 
> loop: load from src reg to temp reg
> store from temp reg to dest reg
> increment src reg
> increment dest reg
> jmp loop

it's a start but there can be more ways and optimisations,
in particular depending on byte/half-word/word/Doubleword size
and alignemnt.

Also look at "Duff's device"
https://en.wikipedia.org/wiki/Duff%27s_device

and of course you can unroll to any degree you like
to boost the bandwidth.

> I’m thinking with at least a four stage pipeline with forwarding, at
> steady state - we’d be storing a byte every cycle?…
it depends if the blocks are aligned (and relatively aligned) as well.

The startup and trailing parts are also relative to the block size,
just like with vector machines.

> So memcpy - probably not well justified…
it depends !

> Any thoughts?
it's a whole can of worms ;-)

yg