[libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=120

--- Comment #24 from Michael Nolan <mtnolan2640 at gmail.com> ---
> second (minor) thing, you'd created a Signal "sign" and then had
> immediately overwritten it with a python variable *also* named
> "sign" which was the result of the Mux().

Oh, I see what you mean now.

    sign = Signal()        # 1
    sign = Mux(op[0],...)  # 2
    sign = Mux(op[1],...)  # 3

I thought you were referring to lines 2 and 3 overwriting sign, not line 1
being overwritten.

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