[libre-riscv-dev] [Bug 153] Top-level for NLNet 2019.10 ASIC Cell Libraries Project.

Staf Verhaegen staf at fibraservi.eu
Sat Jan 11 11:41:31 GMT 2020

bugzilla-daemon at libre-riscv.org schreef op vr 10-01-2020 om 19:04 [+0000]:
> http://bugs.libre-riscv.org/show_bug.cgi?id=153
> --- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---Staf, could you describe what the tasks are, in general? Basically, this ispretty much exactly the list of tasks submitted in the NLNet Proposal.  we canthen begin breaking them down into tasks, and assigned a budget to each.  Thenthe process is: that list gets submitted to NLNet as a schedule on theMemorandum of Understanding, and future payments can be submitted.
> it's important to note that each milestone *can* be further sub-divided, theyare very flexible.  so the "granularity" of these initial milestones does *not*have to be to the absolute minutae: just top-level is good.

Hi Luke and list,

My project is not a libre-riscv only project but uses it as test driver for the development. My development will be done on Chips4Makers on gitlab and on the LIP6 repository. I will do my own internal task management coordinated with NLNet directly.
Of course when milestones are reached for the project it will also be reported on this list.

There are two tape-out deadlines in the project though:
- May 13 tape-out of a 0.18um test chip. This will test the development on standard cell, IO cells and SRAM. This uses so called mini at SIC tapeouts which are only organized twice a year so if we don't get the deadline we get problems in doing the work this year. So this is a hard deadline. This is mainly low-level development not directly related to libre SOC. I will send separate mail on aligning standard cell development with the needs of the libre SOC project.
- Tape-out of a libre SOC test chip in 0.18um. This tape-out is only to be done after the first test chip has been successfully tested. It takes around 3 months to get a chip after tape-out and the testing itself will also take several weeks. Normal size tape-outs are organized about every month; last tape-out deadline for this year is 25 November, but if the moon and sun are right we may be able to tape-out on 28 October. This chip is then planned to contain a (slimmed down) version of the libre SOC chip. So the design is planned to come from the libre SOC project and the P&R to be done by Coriolis software from LIP6. So this task will be mainly between the libre-riscv people and LIP6; my main involvement will be to ensure that the chip can be easily tested.


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