[libre-riscv-dev] Needed standard cell development for libre SOC

[Jean-Paul Chaput]

Hello All,

On Sat, 2020-01-11 at 12:42 +0100, Staf Verhaegen wrote:
> All,
> 
> As said in other mail I will be doing standard cell development on my NLNet
> project. In discussions I had before with Luke it was mentioned that there
> may be need for specific standard cells for certain look-up tables maybe
> coupled with a custom  place-and-route procedure. With current synthesis and
> place-and-route tools this is typically not how one works. There one normally
> just writes the RTL code and leaves everything to the synthesis and place-
> and-route tool.

  I would make some refinement here. The direct synthesis then P&R is good
  if there is no regularity whatsoever in your design. On the opposite you
  have RAM block which are highly regular and that are make by generators
  ("tilers" like OpenRAM). And you have "in between". Depending on the
  regularity of your block it may or may not be useful to create a
  generator. You can see an example of such generator
  in alliance-check-toolkit/benchs/RingOscillator. The generator can
  perform the P&R or just the placement. All written in Python.
   
> We thus need example design code that shows the special need so me and Jean-
> Paul from LIP6 can have a look at how to best handle it from standard cell
> and place-and-route point of view.

  Yes. I totally agree.

  Best regards,
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