July 2019 Archives by thread

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Starting: Mon Jul 1 12:15:28 BST 2019
Ending: Wed Jul 31 21:04:44 BST 2019
Messages: 325

[libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
- [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
  - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] [OT] fine structure constant Hendrik Boom
    - [libre-riscv-dev] [OT] fine structure constant Jacob Lifshay
    - [libre-riscv-dev] [OT] fine structure constant Luke Kenneth Casson Leighton
    - [libre-riscv-dev] [OT] fine structure constant Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
- [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
  - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Jacob Lifshay
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
    - [libre-riscv-dev] div/mod algorithm written in python Luke Kenneth Casson Leighton
[libre-riscv-dev] sv.setvl encoding Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 99] IEEE754 *pipelined* FPDIV unit needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] more variable naming improvements Jacob Lifshay
- [libre-riscv-dev] more variable naming improvements Luke Kenneth Casson Leighton
  - [libre-riscv-dev] more variable naming improvements Luke Kenneth Casson Leighton
    - [libre-riscv-dev] more variable naming improvements Luke Kenneth Casson Leighton
    - [libre-riscv-dev] more variable naming improvements Jacob Lifshay
    - [libre-riscv-dev] more variable naming improvements Luke Kenneth Casson Leighton
[libre-riscv-dev] IEEE754 FVCT Luke Kenneth Casson Leighton
- [libre-riscv-dev] IEEE754 FVCT Luke Kenneth Casson Leighton
  - [libre-riscv-dev] IEEE754 FVCT Luke Kenneth Casson Leighton
  - [libre-riscv-dev] IEEE754 FVCT Luke Kenneth Casson Leighton
  - [libre-riscv-dev] IEEE754 FVCT Luke Kenneth Casson Leighton
[libre-riscv-dev] random testing is insufficient Jacob Lifshay
- [libre-riscv-dev] random testing is insufficient Jacob Lifshay
- [libre-riscv-dev] random testing is insufficient Luke Kenneth Casson Leighton
  - [libre-riscv-dev] random testing is insufficient Jacob Lifshay
    - [libre-riscv-dev] random testing is insufficient Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 107] New: IEEE754 FPU FCVT "downconversion" needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 107] IEEE754 FPU FCVT "downconversion" needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 108] New: IEEE754 FPU FCVT "upconversion" needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 108] IEEE754 FPU FCVT "upconversion" needed bugzilla-daemon at libre-riscv.org
  - [libre-riscv-dev] [Bug 108] IEEE754 FPU FCVT "upconversion" needed Luke Kenneth Casson Leighton
[libre-riscv-dev] FPNumBaseRecord has extra signal Jacob Lifshay
- [libre-riscv-dev] FPNumBaseRecord has extra signal Luke Kenneth Casson Leighton
[libre-riscv-dev] Change pspec to class hierarchy Jacob Lifshay
- [libre-riscv-dev] Change pspec to class hierarchy Luke Kenneth Casson Leighton
  - [libre-riscv-dev] Change pspec to class hierarchy Luke Kenneth Casson Leighton
    - [libre-riscv-dev] Change pspec to class hierarchy Jacob Lifshay
    - [libre-riscv-dev] Change pspec to class hierarchy Luke Kenneth Casson Leighton
    - [libre-riscv-dev] Change pspec to class hierarchy Jacob Lifshay
    - [libre-riscv-dev] Change pspec to class hierarchy Luke Kenneth Casson Leighton
[libre-riscv-dev] FP reciprocal sqrt extension proposal Jacob Lifshay
- [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Bill Huffman
  - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Guy Lemieux
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Dan Petrisko
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Tommy Murphy
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Andrew Waterman
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Andrew Waterman
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Guy Lemieux
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Bruce Hoult
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Guy Lemieux
- [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Jacob Lifshay
  - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Dan Petrisko
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Tommy Murphy
  - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Guy Lemieux
    - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Dan Petrisko
  - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Jacob Lifshay
- [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Jacob Lifshay
- [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal lkcl
- [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal lkcl
  - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Jacob Lifshay
- [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal lkcl
  - [libre-riscv-dev] [isa-dev] FP reciprocal sqrt extension proposal Andrew Waterman
[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 109] New: check if FPNumBaseRecord.v is needed and synchronize with eq and __iter__ bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 110] New: RISC-V FP Reciprocal (inverse) square root ISA extension needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] fpmul Luke Kenneth Casson Leighton
- [libre-riscv-dev] fpmul Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 77] IEEE754 FP "mul" needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] Fwd: Connecting records to records? Samuel Falvo II
- [libre-riscv-dev] Fwd: Connecting records to records? Jacob Lifshay
  - [libre-riscv-dev] Fwd: Connecting records to records? Samuel Falvo II
[libre-riscv-dev] [Bug 97] FP16 mul bug bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 111] New: FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 111] FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 111] FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 111] FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 111] FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 111] FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 111] FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 111] FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 111] FCVT unsigned/signed char/short/int/long (8/16/32/64) to FP16/32/64 needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 112] New: FCVT FP16/32/64 to unsigned/signed char/short/int/long (8/16/32/64) needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] pipeline stage documentation Luke Kenneth Casson Leighton
[libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
- [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Jacob Lifshay
  - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Bill Zorn
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Bill Zorn
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
    - [libre-riscv-dev] bug in sfpy on FP16 integer initialisation Luke Kenneth Casson Leighton
[libre-riscv-dev] old implementation of int to fp in custom cellular automata using golly Jacob Lifshay
- [libre-riscv-dev] old implementation of int to fp in custom cellular automata using golly Jacob Lifshay
- [libre-riscv-dev] old implementation of int to fp in custom cellular automata using golly Luke Kenneth Casson Leighton
[libre-riscv-dev] offtopic: memory safety Jacob Lifshay
- [libre-riscv-dev] offtopic: memory safety Luke Kenneth Casson Leighton
  - [libre-riscv-dev] offtopic: memory safety Jacob Lifshay
    - [libre-riscv-dev] offtopic: memory safety Luke Kenneth Casson Leighton
    - [libre-riscv-dev] offtopic: memory safety Jacob Lifshay
    - [libre-riscv-dev] offtopic: memory safety Luke Kenneth Casson Leighton
    - [libre-riscv-dev] offtopic: memory safety Jacob Lifshay
    - [libre-riscv-dev] offtopic: memory safety Luke Kenneth Casson Leighton
    - [libre-riscv-dev] offtopic: memory safety Hendrik Boom
    - [libre-riscv-dev] offtopic: memory safety Luke Kenneth Casson Leighton
[libre-riscv-dev] Just reading the spec again Tobias Platen
- [libre-riscv-dev] Just reading the spec again Luke Kenneth Casson Leighton
  - [libre-riscv-dev] Just reading the spec again Jacob Lifshay
    - [libre-riscv-dev] Just reading the spec again Luke Kenneth Casson Leighton
    - [libre-riscv-dev] Just reading the spec again Tobias Platen
    - [libre-riscv-dev] Just reading the spec again Luke Kenneth Casson Leighton
    - [libre-riscv-dev] Just reading the spec again Luke Kenneth Casson Leighton
    - [libre-riscv-dev] Just reading the spec again Jacob Lifshay
    - [libre-riscv-dev] Just reading the spec again Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 113] New: FCVT unit tests have too great a dynamic range bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] fcvt and exponent/mantissa shifting Luke Kenneth Casson Leighton
[libre-riscv-dev] https://www.unrealengine.com/en-US/megagrants Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 44] IEEE754 FPU inverse (reciprocal) sqrt bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] UnusedElaboratable when running testbench Tobias Platen
- [libre-riscv-dev] UnusedElaboratable when running testbench Luke Kenneth Casson Leighton
- [libre-riscv-dev] UnusedElaboratable when running testbench Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 114] New: reservation station "feedback" for further processing (FP64) bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 115] New: SIMD ALUs needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 116] New: Integer ADD/MUL/DIV operations needed (using FP bypass). SIMD as well bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 117] New: RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 117] RISCV FCLASS instruction needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 118] New: FP Flags are needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 119] New: Zero and sign extension blocks are needed, FP.and INT bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 48] Complete IEEE754 floating point pipeline bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] gflops Jacob Lifshay
- [libre-riscv-dev] gflops Luke Kenneth Casson Leighton
  - [libre-riscv-dev] gflops Jacob Lifshay
    - [libre-riscv-dev] gflops Jacob Lifshay
    - [libre-riscv-dev] gflops Luke Kenneth Casson Leighton
    - [libre-riscv-dev] gflops Jacob Lifshay
[libre-riscv-dev] [Bug 120] New: implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 120] implement RISC-V FSGNJ instruction bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 121] New: refactor FP exponent naming bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 122] New: FP software emulation needed, bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 122] FP software emulation needed, bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 122] FP software emulation needed, bugzilla-daemon at libre-riscv.org
  - [libre-riscv-dev] [Bug 122] FP software emulation needed, Luke Kenneth Casson Leighton
  - [libre-riscv-dev] [Bug 122] FP software emulation needed, Luke Kenneth Casson Leighton
- [libre-riscv-dev] [Bug 122] FP software emulation needed, bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 123] New: IEEE754 FPU FMAC needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 124] New: add dynamically removable/insertable pipeline registers to div pipe to allow high clock speeds bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 125] New: need NaN unboxing operation bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] number of stages just increased to 6 per pipe-stage Luke Kenneth Casson Leighton
- [libre-riscv-dev] number of stages just increased to 6 per pipe-stage Jacob Lifshay
  - [libre-riscv-dev] number of stages just increased to 6 per pipe-stage Jacob Lifshay
    - [libre-riscv-dev] number of stages just increased to 6 per pipe-stage Luke Kenneth Casson Leighton
[libre-riscv-dev] KCP53010 in danger Samuel Falvo II
- [libre-riscv-dev] KCP53010 in danger Luke Kenneth Casson Leighton
[libre-riscv-dev] [Bug 126] New: Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 126] Make Div core conditional (enable signal) bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] [Bug 101] IEEE754 pipeline "go_die" (Computation Unit Cancellation) needed bugzilla-daemon at libre-riscv.org
- [libre-riscv-dev] [Bug 101] IEEE754 pipeline "go_die" (Computation Unit Cancellation) needed bugzilla-daemon at libre-riscv.org
[libre-riscv-dev] mind melting meta classing Luke Kenneth Casson Leighton
[libre-riscv-dev] big cleanup / reorg Luke Kenneth Casson Leighton
- [libre-riscv-dev] big cleanup / reorg Luke Kenneth Casson Leighton

Last message date: Wed Jul 31 21:04:44 BST 2019
Archived on: Wed Jul 31 21:04:46 BST 2019

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